1. Technical Field
The disclosure relates to a semiconductor package, and more particularly, to a single or stacked semiconductor package to enable high integration of semiconductor chips.
2. Description of the Related Art
Assembling technology for manufacturing semiconductor packages has been greatly developed with the advancement of technology for highly integrated, thin semiconductor devices. In particular, the sizes of semiconductor packages have been greatly reduced to achieve semiconductor products that are compact and light. Modern semiconductor products require a high capacity semiconductor package. Thus, a stacked semiconductor package formed of a stack of a plurality of semiconductor packages or a multi-chip semiconductor package including a plurality of semiconductor chips is used.
FIGS. 1 and 2 are cross-sectional views of conventional semiconductor packages. Referring to FIG. 1, in a conventional semiconductor package 10, a molding resin 16 exists on a semiconductor chip 14 and underneath a chip mounting pad 12, and the semiconductor chip 14 is mounted on the chip mounting pad 12 using an adhesive 13. In other words, the molding resin 16 encloses the semiconductor chip 14, the chip mounting pad 12, and wires 15. It is important that the molding resin 16 fully enclose the top of the semiconductor chip 14 and wires 15 to protect these components from physical damage. Further, wires 15 are typically formed in a loop shape in order to improve the strength of the electrical connection. This means that the molding resin 16 has to be thick enough to enclose the full height of the loops in the wires 15. Thus, the semiconductor package 10 is thick due to the thickness of the molding resin 16. In addition, leads 11 protrude from sides of the molding resin 16 and extend below the molding resin 16 to mount the semiconductor package 10 on a circuit board (not shown). Thus, the size of the semiconductor package 10 is further increased.
Referring to FIG. 2, a semiconductor package 20 has a structure in which lower and upper semiconductor packages 20a and 20b are stacked. The lower and upper semiconductor packages 20a and 20b may refer to the semiconductor package 10 illustrated in FIG. 1. However, leads 11a and 11b may be deformed to be connected to each other, The total thickness of the semiconductor package 20 increases with increases in the thicknesses of the lower and upper semiconductor packages 20a and 20b. 
To solve these problems, a method of forming leads of a semiconductor package to be parallel with the molding resin has been suggested. However, a stack structure of such semiconductor packages has a problem of low reliability of the electrical connection between leads of the upper and lower semiconductor packages. Furthermore, it is difficult for a plurality of semiconductor chips to be mounted due to the disposition of the leads of the upper and lower semiconductor packages.